1. Field of the Invention
This invention relates generally to data processing systems and more particularly to computer memory systems wherein the storage of information is maintained by physical properties which are subject to deterioration.
2. Description of the Prior Art
Electronic data processing systems have grown since their inception in size, speed and complexity. With their growth there has been an ever increasing demand for greater memory storage capacity which at the same time is low in cost and weight and occupies a minimum of space. To answer these demands, there is a trend to an ever increasing use of metal-oxide-semiconductor (MOS) memory elements. The memory elements themselves are typically composed of several interacting devices in which the formation is maintained in the form of a stored charge. Because of leakage currents and other effects, this charge must be periodically restored or refreshed to prevent loss of the information.
Thus, the physical property, which is the analog of the information, must be periodically refreshed. Several techniques and apparatuses have been devised for controlling the refreshing of these volatile memory elements associated with the data processing units. One typical such refresh invention is disclosed in U.S. Pat. No. 3,760,379 issued Sept. 18, 1973 to C. M. Nibby, et al., entitled "Apparatus and Method for Memory Refresh Control" and assigned to the same assignee as the instant application and incorporated by reference.
The metal-oxide-semiconductor random access memories (MOS RAM) have various power requirements which differ depending upon the MOS RAM utilized; however, there is usually one power requirement common to all MOS RAM arrays. This requirement comprises a substrate bias which is generally provided from the power supply of the memory system. Referring to FIG. 2 there is shown a prior art MOS memory refresh system with its power supply. A multivoltage power supply 201 generates and supplies 3 different voltage values to the MOS memory system 200. The VDD voltage supply 202 supplies a typical voltage of plus 12 volts to MOS memory array 206. The VCC voltage supply 203 provides a voltage of plus 5 volts to the MOS memory 206 and also to the Refresh Clock and Logic Circuits 205, and Memory Control and Interface Logic Circuits 207. The minus VBB bias supply 204 provides minus 5 volts to the MOS memory array 206. These voltages are utilized within the memory system 200 to generate the refresh control and refresh clock requirements.
With the advent of mini computers there is an ever increasing emphasis on smaller weight and smaller space requirements and on lower costs. Power supplies in general tend to be heavy and bulky. It is therefore desirable to reduce the size, weight and complexity of the power supply for the refresh control memory system.